Madhusudan Kulkarni and Kalmeshwar N Hosur
SDM College of Engineering and Technology, India

This paper focuses on design and analysis of Current Starved RingVoltageControlledOscillators(CSVCO) for PLL application. The CSVCO circuit is designed and simulated usingGPDK 180nm CMOSTechnology.The CSVCOhas frequency range from 53 MHzto2.348 GHzand power consumption is848μW.The jitter is improved by connecting a D Flip Flop.In this design the maximum time jitter after Dflip flop is 3.1ps and 1.5ps for rising and falling edgerespectivelyand output frequency is from 173MHzto 1.2GHz.The supply voltage VDDis 1.8V

Ring Oscillator,VoltageControlledOscillator(VCO), CurrentStarvedVoltage ControlledOscillator(CSVCO).