A.Murali¹, L.V.Santosh Kumar² and P.Rajesh^3
1KL University and Raghu Engineering College, ²,³Raghu Engineering ,India

This paper gives the comparison of performance of full adder design in terms of area, power and delay in different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more number of transistors compared to GDI. GDI occupies less area compared to all other logic design styles. This paper presents the simulated outcome using Tanner tools and also H-Spice tool which shows power and speed comparison of different full adder designs. All simulations have been performed in 90nm, 45nm and 22nm scaling parameters using Predictive Technology Models in H-Spice tool.

CMOS, SGMOSFET, DGMOSFET, Transmission Gate, GDI, Predictive Technology