P. Koti Lakshmi and Rameshwar Rao
Osmania University, India

Withthe rapid advances in integrated circuit(IC)technologies, number of functions on a chip was increasingat a very fast rate, with which interconnect density is increasing especially in functional logic chips. The on-chip noise affects are increasing and needs to be addressed. In this paper we have implemented a convolutionencoder using a technique that provides highernoise immunity. The encoder circuit is simulated inTanner 15.0 with data rate of 25Mbps and a clock frequency of 250MHz

Noise immune design, Convolutional encoder design.