K. L. V. Ramana Kumari1 , M. Asha Rani2 and N. Balaji3
1VNR Vignana Jyothi Institute of Engineering and Technology, 2Jawaharlal Nehru Technological University, Hydrebad, 3Jawaharlal Nehru Technological University, Vijayanagaram, India
The reduction in feature size increases the probability of manufacturing defect in the IC will result in a faulty chip. A very small defect can easily result in a faulty transistor or interconnecting wire when the feature size is less. Testing is required to guarantee fault-free products, regardless of whether the product is a VLSI device or an electronic system. Simulation is used to verify the correctness of the design. To test n input circuit we required 2n test vectors. As the number inputs of a circuit are more, the exponential growth of the required number of vectors takes much time to test the circuit. It is necessary to find testing methods to reduce test vectors . So here designed an heuristic approach to test the ripple carry adder. Modelsim and Xilinx tools are used to verify and synthesize the design
Ripple carry Adder, Test vectors, Modelsim Simulator
