Jyothi Leonore Dake, Sudheer Kumar Terlapu and K. Lakshmi Divya
SVECW (Autonomous), Bhimavaram, India

In the present work, a low-complexity Digit-Serial/parallel Multiplier over Finite Field is proposed. It is employed in applications like cryptography for data encryption and decryptionto deal with discrete mathematical andarithmetic structures. The proposedmultiplier utilizes a redundant representation because of their free squaring and modular reduction. The proposed 10-bit multiplier is simulated and synthesized using Xilinx VerilogHDL. It is evident from the simulation results that the multiplier has significantly low area and power when compared to the previous structures using the same representation.

Digit-Serial, Finite Field multiplication, Redundant Basis.