Gurunadha.Ravva
Jawaharlal Nehru Technological University, Vijayanagaram, India

Adders are one of the most critical arithmetic circuits in a system and their throughput affects the overall performance of the system. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. In this paper, we proposed an area-efficient carry select adder by sharing the common Boolean logic term. After logic optimization and sharing partial circuit, we only need one XOR gate and one inverter gate for sum generation. Through the multiplexer, we can select the final-sum only and for carry selection we need only one AND gate and one OR gate. Based on this modification 16-, 32-, 64-, and 128-bit CSLA architecture have beendeveloped and compared with the conventional CSLA architecture.The proposed design greatly reduces the area compared to other CSLAs. From this improvement, the gate count of a 128-bit carry select adder can be reduced from 3320 to 1664. The proposed structure is implemented in Artix-7 FPGA. Compared with the proposed design, the conventional CSLA has 65.80% less area.

Carry Select Adder, Area-Efficient