Design of ALU using 2T XOR gate and Decoder


Aiyyappu Surendra babu, Ashokkumar.N
Sree Vidya nikethan Engineering College, Tirupati, India


A design of Arithmetic and Logic Unit (ALU) with modified Gate Diffusion Input (m-GDI) as well as a design of ALU with 2T XOR GATE and DECODER are proposed in this paper. The use of modified Gate Diffusion Input in these techniques reduces the delay path, power consumption and area, as well as the number of transistors used. The power consumption is extremely low, resulting in a smaller footprint and a shorter delay path. The major components used in these techniques are the 2T XOR Gate in Digital VLSI Design based on Full Adder and Full Subtractor. Major, a fundamental novel The circuit for a 1-to-8 decoder was planned for different logic families before being implemented in an 8-bit Arithmetic and Logic Unit. EDA TANNER and Technique 180 nanometer Technology File are used to model the effects.


Arithmetic and Logic Unit(ALU) , VLSI Design, 2T XOR, DSCH 3.5, Modified Gate Diffusion Input (GDI)Tanner EDA and Technology File 180nm, and Verilog.